Honors

  • 2014 Second Prize, ACM/IEEE ICCAD and MOE CAD Contest on Incremental Timing Driven Placement (with W.-C. Wu et al.)
  • 2014 First Prize, ACM ISPD Detailed Routing-Driven Placement Contest (with S. Liu et al.)
  • 2008 and 2009 NCTU Excellent Teaching Awards
  • 2007 MOE SoC Consortium Outstanding Service Award
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publications
Publications


    • Book Chapter
        1. H.-M. Chen, D.F. Wong, H. Zhou, F.Y. Young, H.H. Yang, and N. Sherwani,
          “Integrated Floorplanning and Interconnect Planning,” in Layout
          Optimization in VLSI Designs
          , Kluwer Academic Publishers, 2001
        2. K.-C. Wang and H.-M. Chen, “Multilevel Large-Scale Modules Floorplanning/Placement with
          Improved Neighborhood Exchange in Simulated Annealing,” in Simulated Annealing, Theory with
          Applications
          , Sciyo, 2010

 

    • ACM/IEEE Journal Papers [SCI, EI]
        1. H.-M. Chen, L.-D. Huang, I-M. Liu, and D.F. Wong, “Simultaneous Power
          Supply Planning and Noise Avoidance in Floorplan Design,” IEEE
          Transactions on Computer-Aided Design of Integrated Circuits and Systems
          ,
          v.24, no.4, pp.578-587, April 2005 (TCAD-Apr-05)
        2. H.-M. Chen, I-M. Liu, and D.F. Wong, “I/O Clustering in Design Cost and Performance
          Optimization for Flip-Chip Design,” IEEE
          Transactions on Computer-Aided Design of Integrated Circuits and Systems
          ,
          v.25, no.11, pp.2552-2556, November 2006 (TCAD-Nov-06)
        3. Chia-Yi Chang and H.-M. Chen, “Design Migration from Peripheral ASIC Design to
          Area-IO Flip-Chip Design by Chip I/O Planning and Legalization,”
          IEEE Transactions on Very Large Scale Integration Systems,
          v.16, no.1, pp.108-112, January 2008
          (TVLSI-Jan-08)
        4. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “Effective Decap Insertion in Area-Array
          SoC Floorplan Design,” ACM Transactions on
          Design Automation of Electronic Systems
          , v.13, no.4, article 66, September 2008
          (TODAES-Sep-08)
        5. R.-J. Lee and H.-M. Chen, “Fast Flip-Chip Pin-Out Designation Respin
          for Package-Board Codesign,” IEEE Transactions on Very Large
          Scale Integration Systems
          , v.17, no.8, pp.1087-1098, August 2009 (TVLSI-Aug-09)
        6. M.-C. Wu, M.-C. Lu, H.-M. Chen, and J.-Y. Jou, “Performance-Constrained
          Voltage Assignment in Multiple Supply Voltage SoC Floorplanning,” ACM Transactions
          on Design Automation of Electronic Systems
          , 15(1), article 3, December 2009 (TODAES-Dec-09)
        7. C.-Y. Lin, H.-C. Lin, and H.-M. Chen, “On Reducing Test Power and Test Volume
          by Effective Pattern Compression Schemes,” IEEE Transactions on Very Large
          Scale Integration Systems
          , 18(8), pp.1220-1224, August 2010 (TVLSI-Aug-10)
        8. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with System
          Interconnects Optimization for Package-Board Codesign,”
          IEEE Transactions on Very Large Scale Integration Systems, 19(5), May 2011 (TVLSI-May-11)
        9. R.-J. Lee and H.-M. Chen, “A Study of Row-Based Area-Array I/O Design Planning in Concurrent
          Chip-Package Design Flow,” ACM Transactions on Design Automation of Electronic Systems, 18(2),
          article 30, March 2013 (TODAES-Mar-13)
        10. C.-Y. Chin, C.-Y. Kuan, T.-Y. Tsai, H.-M. Chen and Y. Kajitani, “Escaped Boundary Pins
          Routing for High Speed Boards,” IEEE Transactions on Computer-Aided Design of Integrated
          Circuits and Systems
          , 32(3), March 2013 (TCAD-Mar-13)
        11. S.-Y. Liu, W.-T. Lo, C.-J. Lee, and H.-M. Chen, “Agglomerative- Based Flip-Flop Merging and
          Relocation for Signal Wirelength and Clock Tree Optimization,” ACM Transactions on Design
          Automation of Electronic Systems
          , 18(3) Article 40, July 2013 (TODAES-Jul-13)
        12. R.-J. Lee, H.-W. Hsu and H.-M. Chen, “Board- and Chip-Aware Package Wire Planning,” IEEE
          Transactions on Very Large Scale Integration Systems
          , 21(8), August 2013 (TVLSI-Aug-13)
        13. S.-Y. Liu, R.-G. Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen, “A Fast Thermal Aware
          Placement with Accurate Thermal Analysis Based on Green Function,” IEEE Transactions on
          Very Large Scale Integration Systems
          , 22(6), June 2014 (TVLSI-Jun-14)
        14. S.-Y. Liu, C.-H. Chang, H.-M. Chen and T.-Y. Ho, “ACER: An Agglomerative Clustering Based
          Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips,” IEEE Transactions
          on Computer-Aided Design of Integrated Circuits and Systems
          , 33(9), September 2014 (TCAD-Sep-14)
        15. C.-K. Wang, Y.-C. Chang, H.-M. Chen, C.-Y. Chin, “Clock Tree Synthesis Considering Slew
          Effect on Supply Voltage Variation,” ACM Transactions on Design Automation of Electronics
          Systems
          , 20(1) Article 3, November 2014 (TODAES-Nov-14)
        16. P.-C. Pan, C.-Y. Chin, H.-M. Chen, T.-C. Chen, C.-C. Lee, and J.-C. Lin, “A Fast Prototyp-
          ing Framework for Analog Layout Migration with Planar Preservation,” IEEE Transactions on
          Computer-Aided Design of Integrated Circuits and Systems
          , 34(9), September 2015 (TCAD-Sep-15)
        17. G.-R. Lu, C.-H. Kuo, K.-C. Chiang, A. Banerjee and B. B. Bhattacharya, T.-Y. Ho, and H.-M.
          Chen, “Flexible Droplet Routing in Active-Matrix Based Digital Microfluidic Biochips,” ACM
          Transactions on Design Automation of Electronic Systems
          , 23(3), April 2018 (TODAES-Apr-18)
        18. G.-R. Lu, A. Banerjee, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “Reliability Hardening
          Mechanisms in Cyber-Physical Digital-Microfluidic Biochips,” ACM Journal on Emerging Tech-
          nologies in Computing
          , 14(3), October 2018 (JETC-Oct-18)

 

 

    • Other Journal Papers

[SCI/EI]

        1. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “An Effective Decap Insertion Method
          Considering Power Supply Noise During Floorplanning,” January 2008, Journal of
          Information Science and Engineering
          (JISE-Jan-08)
        2. Bruce Tseng and H.-M. Chen, “Dual-Vdd Voltage Island-Aware Buffered Routing
          Tree Construction,” International Journal of Electrical Engineering, April 2008
          (IJEE-Apr-08)
        3. Y.-C. Lin, H.-A. Chien, C.-C. Shih, and H.-M. Chen, “A Multi-layer Obstacles-Avoiding
          Router Using X-Architecture,” WSEAS Transaction on Circuits and Systems, Issue 8,
          Volume 7, August 2008
        4. C.-Y. Lin, H.-C. Lin, and H.-M. Chen, “A Methodology with Selective Pattern Compression
          Schemes on Reducing Test Power and Test Volume,” International Journal of
          Electrical Engineering
          , 17(1), pp. 75-88, January 2010 (IJEE-Jan-10)
        5. C.-Y. Lin, L.-C. Hsu, and H.-M. Chen, “On Reducing Test Power, Volume and Routing Cost by Chain
          Reordering and Test Compression Techniques,” IEICE Transactions on Electronics, vol.
          E93-C no. 3, pp.369-378, March 2010 (IEICE-Mar-10)
        6. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “Design Planning with 3D-Via Optimization in Alternative
          Stacking Integrated Circuits,” Journal of Information Science and Engineering, January 2011 (JISE-Jan-11)
        7. C.-Y. Lin and H.-M. Chen, “A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost,”
          Journal of Information Science and Engineering, November 2011 (JISE-Nov-11)
        8. C.-H. Lu, H.-M. Chen, C.-N. Liu, W.-Y. Shih, “Package Routability and IR-Drop-Aware Finger/Pad
          Planning for Single Chip and Stacking IC Designs,” Integration, the VLSI Journal, May
          2012 (Integration-May-12)
        9. J.-D. Li, C.-H. Kuo, G.-R. Lu, S.-J. Wang, Katherine S.-M. Li, T.-Y. Ho, H.-M. Chen and S. Hu,
          “Co-placement Optimization in Sensor-reusable Cyber-physical Digital Microfluidic Biochips, ”
          Microelectronics Journal 83, pp. 185-196, January, 2019

 

    • ACM/IEEE Conference/Workshop Papers
        1. H.-M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, and N. Sherwani,
          “Integrated Floorplanning and Interconnect Planning,”
          IEEE/ACM ICCAD-99, pp. 356-359, November 1999.
        2. I-Min Liu, H.-M. Chen, T.-L. Chou, A. Aziz, and D.F. Wong,
          “Integrated Power Supply Planning and Floorplanning,” ACM/IEEE ASP-DAC-01, pp. 589-594,
          January 2001.
        3. H.-M. Chen, D.F. Wong, W.-K. Mak, and H.H. Yang, “Faster and
          More Accurate Wiring Evaluation for Interconnect-Centric Floorplanning,”
          ACM GLSVLSI-01, pp. 62-67, March 2001.
        4. H.-M. Chen, L.-D. Huang, I-M. Liu, M. Lai, and D.F. Wong, ”
          Floorplanning with Power Supply Noise Avoidance,” ACM/IEEE ASP-DAC-03,
          pp. 427-430, January 2003
        5. L.-D. Huang, H.-M. Chen, and D.F. Wong, “Global Wire Bus Configuration
          with Minimum Delay Uncertainty,” IEEE/ACM DATE-03, pp. 50-55, April 2003
        6. H.-M. Chen, I-M. Liu, M.D.F. Wong, M. Shao, and L.-D. Huang, ”
          I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design,”
          IEEE ICCD-04, pp. 562-567, October 2004
        7. M. Shao, Y. Gao, L. Yuan, M.D.F. Wong, and H.-M. Chen, “Current Calculation on
          Signal Interconnects,” ISQED-05, pp.580-585, March 2005
        8. L.-C. Hsu and H.-M. Chen, “On Optimizing Scan
          Testing Power and Routing Cost in Scan Chain Design,” ISQED-06, pp.451-456,
          March 2006
        9. C.-Y. Chang and H.-M. Chen, “Design Migration from Peripheral
          ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization,”
          IEEE VLSI-DAT-06, pp.147-150, April 2006
        10. K.-C. Wang and H.-M. Chen, “Multilevel Large-Scale Modules
          Placement with Refined Neighborhood Exchange,” IEEE VLSI-DAT-06, pp.235-238,
          April 2006
        11. H.-L. Chen and H.-M. Chen, “On Achieving Low-Power SoC
          Clock Tree Synthesis by Transition Time Planning via Buffer Library Study,”
          IEEE SOCC-06, pp.203-206, September 2006
        12. M.-C. Lu, M.-C. Wu, H.-M. Chen, and H.-R. Jiang, “Performance
          Constraints Aware Voltage Island Generation in SoC Floorplan
          Design,” IEEE SOCC-06, pp.211-214, September 2006
        13. R.-J. Lee, M.-F. Lai, and H.-M. Chen, “Fast Flip-Chip Pin-Out
          Designation by Pin-Block Design and Floorplanning for Package-Board
          Codesign,” ACM/IEEE ASP-DAC-07, pp.804-809, January 2007
        14. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “On Increasing
          Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design,”
          ACM/IEEE ASP-DAC-07, pp.792-797, January 2007
        15. C.-Y. Chen, J.-D. Huang, and H.-M. Chen, “Microarchitecture-Aware
          Floorplanning for Processor Performance Optimization,”
          IEEE VLSI-DAT-07, pp.116-119, April 2007
        16. C.-Y. Yeh, H.-M. Chen, L.-D. Huang, W.-T. Wei, C.-H. Lu, and C.-N. Liu,
          “Using Power Gating Techniques in Area-Array SoC Floorplan Design,”
          IEEE SOCC-07, pp.233-236, September 2007
        17. C.-Y. Lin and H.-M. Chen, “A Selective Pattern-Compression
          Scheme for Power and Test-Data Reduction,” IEEE/ACM ICCAD-07, pp. 520-525,
          November 2007
        18. M.-F. Lai and H.-M. Chen, “An Implementation of
          Performance-Driven Block and I/O Placement for Chip-Package Codesign,”
          ISQED-08, pp.604-607, March 2008
        19. Bruce Tseng and H.-M. Chen, “Blockage and Voltage
          Island-Aware Dual-Vdd Buffered Tree Construction,” ACM ISPD-08, pp.23-30,
          April 2008
        20. C.-H. Shui and H.-M. Chen, “On Minimizing Topography Variation in Multi-Layer
          Oxide CMP Manufacturability,” IEEE VLSI-DAT-08, April 2008 (Best
          Paper Award Nominee)
        21. L.-C. Wei, H.-M. Chen, L.-D. Huang, and S. Xu, “Efficient and Optimal
          Post-Layout Double-Cut Via Insertion by Network Relaxation and Min-Cost Maximum
          Flow,” ACM GLSVLSI-08, May 2008
        22. H.-H. Pan, H.-M. Chen, and C.-Y. Chang, “Buffer/Flip-Flop Block Planning for
          Power-Integrity-Driven Floorplanning,” ISQED-09, March 2009
        23. C.-H. Lu, H.-M. Chen, C.-N. Liu, and W.-Y. Shih, “Package Routability- and IR-Drop-Aware
          Finger/Pad Assignment in Chip-Package Co-Design,” IEEE/ACM DATE-09, April 2009
        24. Y.-L. Co, H.-M. Chen, and Y.-K. Cheng, “Coupling- and ECP-Aware Metal Fill for Improving
          Layout Uniformity in Copper CMP,” IEEE VLSI-DAT-09, April 2009
          (Best Paper Award Nominee)
        25. B.-C. Chen, H.-M. Chen, L.-D. Huang, and P.-C. Pan, “A Stochastic-Based Efficient Critical Area
          Extractor on OpenAccess Platform,” ACM GLSVLSI-09, May 2009
        26. C.-H. Lin and H.-M. Chen, “On Minimizing Various Sources of Noise and Meeting Symmetry
          Constraint in Mixed-Signal SoC Floorplan Design,” ASQED-09, July 2009
        27. F.-Y. Fan, H.-M. Chen, and I-M. Liu, “On Preserving Signal Integrity in Technology Mapping,”
          ACM/IEEE IWLS-09, July 2009
        28. C.-C. Hsiao and H.-M. Chen, “On Distinguishing Process Corners for Yield Enhancement in
          Memory Compiler Generated SRAM,” IEEE MTDT-09, August 2009
        29. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with Chip-Package Interconnects
          Optimization,” IEEE EDAPS-09, December 2009
        30. R.-J. Lee and H.-M. Chen, “Novel I/O-Bump Design and Optimization for Chip-Package Codesign,”
          IEEE EDAPS-09, December 2009
        31. F.-Y. Fan, H.-M. Chen, and I-M. Liu, “Technology Mapping with Crosstalk Noise Avoidance,”
          ACM/IEEE ASP-DAC-10, January 2010
        32. C.-Y. Lin and H.-M. Chen, “A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction,”
          ISQED-10, March 2010
        33. H.-Y. Li, Iris H.-R. Jiang, and H.-M. Chen, “Simultaneous Voltage Island Generation and Floorplanning,”
          IEEE SOCC-10, September 2010
        34. Y.-A. Shih, T.-H. Tsai, and H.-M. Chen, “Path-Based Cell Flipping Optimization for Wirelength
          Reduction and Routability,” IEEE TENCON-10, November 2010
        35. C.-Y. Lin, Y.-W. Chen, W.-J. Chen, and H.-M. Chen, “Fast Detection and Analysis Schemes for
          System-in-Package in the Presence of RAM,” IEEE Workshop on RTL and High Level Testing,
          December 2010
        36. K.-S. Lin, H.-W. Hsu, R.-J. Lee, and H.-M. Chen, “Area-I/O RDL Routing for Chip-Package
          Codesign Considering Regional Assignment,” IEEE EDAPS-10, December 2010
        37. R.-J. Lee and H.-M. Chen, “Row-Based Area-Array I/O Design Planning in Concurrent Chip-
          Package Design Flow,” ACM/IEEE ASP-DAC-11, January 2011
        38. C.-C. Tsai, T.-H. Lin, S.-H. Tsai, and H.-M. Chen, “Clock Planning for Multi-Voltage and Multi-
          Mode Designs,” ISQED-11, March 2011
        39. K.-H. Meng, P.-C. Pan, and H.-M. Chen, “Integrated Hierarchical Synthesis of Analog/RF Cir-
          cuits with Accurate Performance Mapping,” ISQED-11, March 2011
        40. M.-C. Wu, H.-M. Chen, and J.-Y. Jou, “Mixed Non-Rectangular Block Packing for Non-Manhattan
          Layout Architectures,” ISQED-11, March 2011
        41. Y.-R. Chen, H.-M. Chen, and S.-Y. Liu, “Z-Cut First Timing Driven Placement for TSV-Based
          3D ICs,” IEEE/ACM DATE 3D Integration Workshop, March 2011
        42. T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan, H.-M. Chen, and Y. Kajitani, ”
          On Routing Fixed Escaped Boundary Pins for High Speed Boards,” IEEE/ACM DATE-11, March 2011
        43. C.-Y. Lin, H.-M. Chen, and W.-C. Fang, “A Low Noise and Robust 3D System-in-Package Test
          Scheme for Optical Biosensor,” IEEE/NIH Life Science Systems and Applications Workshop (LiSSA-11),
          April 2011
        44. Y.-R. Chen, H.-M. Chen, and S.-Y. Liu, “TSV-Based 3D-IC Placement for Timing Optimization,” IEEE SOCC-11, September, 2011
        45. Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen, “Fast Analog
          Layout Prototyping for Nanometer Design Migration,” IEEE/ACM ICCAD-11, November 2011
        46. Y.-C. Chang, C.-K. Wang and H.-M. Chen, “Slew Rate Aware Lower Power and More Robust
          Clock Tree Construction,” ACM TAU-12, January 2012
        47. S. Aroonsantidecha, S.-Y. Liu, C.-Y. Chin, and H.-M. Chen, “A Fast Thermal Aware Placement
          with Accurate Thermal Analysis Based on Green Function,” ACM/IEEE ASP-DAC-12, January 2012
        48. Y.-C. Chang, C.-K. Wang and H.-M. Chen, “On Constructing Low Power and Robust Clock Tree
          via Slew Budgeting,” ACM ISPD-12, March 2012
        49. C.-J. Lee, S.-Y. Liu, C.-C. Huang, H.-M. Chen, C.-T. Lin, and C.-H. Lee, “Hierarchical Power
          Network Synthesis for Multiple Power Domain Designs,” ISQED-12, March 2012
        50. H.-W. Hsu, M.-L. Chen, H.-M. Chen, and H. Chen, “On Effective Flip-Chip Routing via Pseudo
          Single Redistribution Layer,” IEEE/ACM DATE-12, March 2012
        51. S.-Y. Liu, C.-J. Lee, and H.-M. Chen, “Agglomerative Based Flip-Flop Merging for Power Optimization,”
          IEEE/ACM DATE-12, March 2012
        52. P.-C. Pan, H.-M. Chen, Y.-K. Cheng, J. Liu and W.-Y. Hu, “Configurable Analog Routing
          Methodology via Technology and Design Constraint Unification,” IEEE/ACM ICCAD-12, November 2012
        53. S.-Y. Liu, R.-G. Luo, and H.-M. Chen, “A Network-Flow Based Algorithm For Power Density
          Mitigation at Post-Placement Stage,” IEEE/ACM DATE-13, March 2013
        54. S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin, C.-H. Lee, “Effective Power Network
          Prototyping via Statistical-Based Clustering and Sequential Linear Programming,” IEEE/ACM DATE-13, March 2013
        55. P.-C. Pan, H.-M. Chen and C.-C. Lin, “PAGE: Parallel Agile Genetic Exploration toward Utmost
          Performance for Analog Circuit Design,” IEEE/ACM DATE-13, March 2013
        56. H.-M. Chen, “On the Way to Practical Tools for Beyond Die Codesign and Integration,”
          ACM ISPD-13, March 2013 (Invited)
        57. C.-C. Chen, W.-C. Wu, C.-Y. Chin, H.-M. Chen, V. Lin, E. Chen, “Mean-time-to-crack Model of
          Microbump Interconnect in FCBGA Package under Thermal Cyclic Test,” IEEE THERMINIC-13, September
          2013
        58. C.-Y. Chin, P.-C. Pan, H.-M. Chen, T.-C. Chen and J.-C. Lin, “Efficient Analog Layout Prototyping
          by Layout Reuse with Routing Preservation,” IEEE/ACM ICCAD-13, November 2013
        59. Y.-J. Lee, H.-M. Chen, and C.-Y. Chin, “On Simultaneous Escape Routing of Length Matching
          Differential Signalings,” IEEE EDAPS-13, December 2013
        60. C.-Y. Chin and H.-M. Chen, “Simultaneous Escape Routing on Multiple Components for Dense
          PCBs,” IEEE EDAPS-13, December 2013
        61. M.-L. Chen, T.-H. Tsai, H.-M. Chen and S.-H. Chen, “Routability-Driven Bump Assignment
          for Chip-Package Co-Design,” ACM/IEEE ASP-DAC-14, January 2014
        62. Y.-E. Chen, T.-H. Tsai, S.-H. Chen and H.-M. Chen,”Cost-Effective Decap Selection for Beyond
          Die Power Integrity,” IEEE/ACM DATE-14, March 2014
        63. Y. Shi and H.-M. Chen, “Memcomputing: the Cape of Good Hope,” IEEE/ACM DATE-14, March 2014
        64. S.-H. Hsu, W.-Z. Chen, J.-P. Zheng, S.-Y. Liu, P.-C. Pan and H.-M. Chen, “An Automatic Synthesis
          Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric
          Programming,” IEEE VLSI-DAT-14, April 2014
        65. C.-C. Huang, C.-T. Lin, W.-S. Liao, C.-J. Lee, H.-M. Chen, C.-H. Lee and D.-M. Kwai,
          “Improving Power Delivery Network Design by Practical Methodologies,” IEEE ICCD-14,
          October 2014
        66. H.-C. Lin, S.-Y. Liu and H.-M. Chen, “Planning and Placing Power Clamps for Effective CDM
          Protection,” IEEE/ACM ICCAD-14, November 2014
        67. S.-Y. Liu, T.-C. Chen, and H.-M. Chen, “An Approach to Anchoring and Placing High Performance
          Custom Digital Designs,” ACM/IEEE ASP-DAC-15, January 2015
        68. C.-K Wang, C.-C. Huang, S.-Y. Liu, C.-Y. Chin, S.-T. Hu, W.-C. Wu and H.-M Chen, “Closing
          the Gap between Global and Detailed Placement: Techniques for Improving Routability,” ACM ISPD-15, March 2015
        69. Y.-H. Hung, S.-H. Fang, H.-M. Chen, S.-M. Chen, C.-T. Lin, and C.-H. Lee, “A New Methodology
          for Noise Sensor Placement Based on Association Rule Mining,” ACM GLSVLSI-16, May 2016 (Best Paper Award Nominee)
        70. C.-H. Kuo, G.-R. Lu, H.-M. Chen, T.-Y. Ho, and S. Hu, “Placement Optimization of Cyber-
          Physical Digital Microfluidic Biochips,” IEEE BioCAS-16, October 2016
        71. G.-R. Lu, G.-M. Huang, A. Banerjee, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen,
          “On Reliability Hardening in Cyber-Physical Digital-Microfluidic Biochips,”
          ACM/IEEE ASP-DAC-17, January 2017
        72. W.-H. Liao, C.-T. Lin, S.-H. Fang, C.-C. Huang, H.-M. Chen, D.-M. Kwai, and Y.-F. Chou,
          “Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization,”
          ACM/IEEE ASP-DAC-17, January 2017 (Invited)
        73. W.-N. Wu, C. Chen, C.-Y. Chin, C.-K. Wang, and H.-M. Chen, “An Analytical Placer for
          Heterogeneous FPGAs via Rough-Placed Packing,” IEEE VLSI-DAT-17, April 2017
        74. S.-H. Fang, C.-T. Lin, W.-H. Liao, C.-C. Huang, L.-C. Chen, H.-M. Chen, I-H. Lee, D.-M. Kwai,
          and Y.-F. Chou, “On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D
          IC,” IEEE ISVLSI-17, July 2017
        75. G.-R. Lu, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “Multi-Level Droplet Routing in
          Active-Matrix Based Digital-Microfluidic Biochips,” ACM/IEEE ASP-DAC-18, January 2018
        76. H.-Y. Chi, H.-Y. Tseng, C.-N. Liu, and H.-M. Chen, “Performance-Preserved Analog
          Routing Methodology via Wire Load Reduction,” ACM/IEEE ASP-DAC-18, January 2018
        77. L.-C. Chen, C.-C. Huang, Y.-L. Chang and H.-M. Chen, “A Learning-Based Methodology for
          Routability Prediction in Placement,” IEEE VLSI-DAT-18, April 2018
        78. A. Patyal, P.-C. Pan, A. Reddy, H.-M. Chen, H.-Y. Chi, and C.-N. Liu, ”
          Analog Placement with Current Flow and Symmetry Constraints using PCP-SP,” ACM/IEEE
          DAC-18
          , June 2018
        79. P.-C. Pan, H.-W. Huang, C.-C. Huang, A. Patyal, H.-M. Chen and T.-Y. Yang, “On Closing
          the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts,”
          SMACD-18, July 2018
        80. B.-H. Jiang and H.-M. Chen, “Extending ML-OARSMT to Net Open Locator with Efficient
          and Effective Boolean Operations,” IEEE/ACM ICCAD-18, November 2018
        81. Asha K A, A. Patyal, and H.-M. Chen, “Generation of PUF-Keys on FPGAs by K-means Frequency
          Clustering,” IEEE AsianHOST-18, December 2018
        82. Y.-H. Chuang, C.-T. Lin, H.-M. Chen, C.-H. Lee and T.-S. Chen, “More Effective Power Network
          Prototyping by Analytical and Centroid Learning,” IEEE ISCAS-19, May 2019
        83. P.-C. Pan, C.-C Huang and H.-M. Chen, “An Efficient Learning-based Approach for Performance
          Exploration on Analog and RF Circuit Synthesis (LBR),” ACM/IEEE DAC-19, June 2019
        84. Y.-H. Chen, H.-Y. Chi, L.-Y. Song, C.-N. Liu and H.-M. Chen, “A Structure-Based Methodol-
          ogy for Analog Layout Generation,” SMACD-19, July 2019 (to appear)
        85. H.-Y. Chi, Z.-J. Lin, C.-H. Hung, C.-N. Liu and H.-M. Chen, “Achieving Routing Integrity in
          Analog Layout Migration via Cartesian Detection Lines,” IEEE/ACM ICCAD-19, November 2019 (to appear)
        86. C.-Y. He, K.-H. Tang, T.-S. Chen, K.-Y. Chang, C.-H. Lin, K. Sato, S.-J. Jou, P.-H. Chen, H.-M.Chen, B.-D. Rong, K. Itoh, “Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-
          5T Cell and Built-in Y Line,” Proc. of IEEE Asian Solid-State Circuits Conference, November

          2019 (ASSCC-19)

        87. J.-R. Jiang, Y.-C. Kuo, Y.-H. Chen, and H.-M. Chen, “On Pre-Assignment Route Prototyping
          for Irregular Bumps on BGA Packages,” Proc. of IEEE/ACM Design, Automation and Test in
          Europe, March 2020 (DATE-20, to appear)
        88. S.-H. Liou, S. Liu, R. Sun and H.-M Chen, “Timing Driven Partition for Multi-FPGA Systems
          with TDM Awareness,” Proc. of ACM International Symposium on Physical Design, March 2020
          (ISPD-20, to appear)
        89. H.-Y. Chang, H.-M. Chen, Y.-C. Kuo, H.-T. Tsai, Simon Y.-H. Chen, J.-R. Jiang, and Y.-Y.
          Chien, “Irregular Bumps Design Planning for Modern Ball Grid Array Packages,” Proc. of IEEE
          Electronic Components and Technology Conference, May 2020 (ECTC-20, to appear)
        90. M.-Y. Huang and H.-M. Chen et al., “A Design Flow for Micro Bump and Stripe Planning
          on Modern Chip-Package Co-Design,” Proc. of IEEE Electronic Components and Technology
          Conference, May 2020 (ECTC-20, to appear)

 

    • Other non-EDA Papers
        1. L. F. Chien , H. T. Pu, M. C. Chen, H.-M. Chen and M. J. Lee, “Natural
          Language Information Retrieval with speech recognition techniques for network
          Chinese resources discovery,” Proceedings of the 1996 International
          Workshop on Information Retrieval with Oriental Languages (IROL 96)
        2. L. F. Chien , M. C. Chen, M. J. Lee , H.-M. Chen, T. Huang and H. T.
          Pu, “Speech and Natural Language Information Retrieval for Real-time Chinese
          Netnews Service,” Proceedings of the 1997 Int. Conf. On Computer Processing
          of Oriental Languages
          , Hong Kong, April 1997 (ICCPOL 97)

 

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Professor  教授

陳宏明 hmchen@mail.nctu.edu.tw


Ph.D. Students 博士班學生

潘艾必(Abhishek Patyal) patyal_abhishek@rediffmail.com
Asha asha.03a@gmail.com
紀浩瑜 doyouknowwhoiam1006@gmail.com


Master Students 碩士班學生

碩二
黃英耀 ian2000770@gmail.com 簡雅瑛 lilyc67a@gmail.com
趙韋同 ddcfei@gmail.com 黃茗榆 mingyu0328@gmail.com
徐立恩 zebra00258@gmail.com 蔡宜珊 sandy970875@gmail.com

.

碩一
陳柏仰 pychen.ee08g@nctu.edu.tw 黃俊維 j7922018@gmail.com
呂揚 k788170@gmail.com 林力宇 davidlin0857@gmail.com
劉泳儀 aamy.11234@gmail.com 何舉文 410423014@gms.ndhu.edu.tw
姜承佑 chfrank9807@gmail.com Thasreefa thasreefaak43@gmail.com

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研究方向

  • Design automation for electronics
  • Learning based methodologies
  • 2.5D/3D ic and package design planning
  • Automation on analog circuit design and layout synthesis
  • Microfluidic biochip layout synthesis

實驗室守則

  • Be happy ^___^
  • passion with coding in EDA !

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Hung-Ming Chen (陳宏明)

Professor and Director (2018-2021)
Institute of Electronics
College of Electrical and Computer Engineering
National Chiao Tung
University,
Hsinchu,Taiwan
E-mail: hmchen@mail.nctu.edu.tw
Office: ED[Engr. Bldg. 4] 407
Voice: +886-3-5731626

Teaching

  • Current Teaching
    • Object-Oriented Programming (Freshmen)
    • Advanced Algorithms (Graduate)
  • Past Teaching
    • Introduction to Comupters and Programming (Freshmen)
    • Assembly Language (Sophomore)
    • Data Structure (Sophomore)
    • Digital Circuits and Systems (with Verilog) (Sophomore)
    • Discrete Mathematics (Sophomore)
    • Introduction to Electronic Design Automation (Junior and Senior)
    • VLSI Design for Manufacturability (Graduate)
    • Special Topics on CAD (Synthesis and Verification) (Graduate)
    • VLSI Physical Design Automation (Graduate)

Research

Services

Last update: July 6, 2019

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